AEIC-7272-S16 quad diff erential line driver separate logic bias and driver bias with tri-state outputs data sheet description these line drivers are pin compatible with 26ls31 in ap- plications where pin 4 = 5v and pin 12 = gnd. internal clamp diodes allow trouble-free operation when driving cable lengths exceeding 100m. split supplies are provided to minimize standby power dissipation in high voltage ap- plications. the logic should be powered from a regulated 5v supply at the vccbias pin. the output stages may then be powered by a separate supply at vccdrivers, up to 30v. output voltage swings of 0.3v to vcc-1.9v are typical. the outputs are protected against shorts to ground, shorts to vcc and to other outputs, by a two-fold scheme of current limiting and thermal shutdown. this assures highly reliable operation in harsh environments. this part is available in 16l soic (pb-free) package. applications ?? encoders ?? industrial controls features ?? supply (bias) voltage range 3.5 v to 30 v ?? operation to 800 khz ?? cmos and ttl compatible inputs ?? separate logic bias and driver supply pins ?? optional single supply operation for moderate power applications ?? high impedance buff ered inputs with hysteresis ?? tri-state outputs ?? 80 ma peak sink/source current pin assignment d in a in a+ a- vcc bias d- d+ vcc drivers c- b- b+ b in gnd c in c+ en- v reg 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
2 table 1. absolute maximum ratings parameters symbol min. max. units test conditions operating temperature range t a -55 125 c supply (driver) voltage range v ccd 4.5 30 v table 2. electrical characteristics unless otherwise specifi ed, t a = 25 c and en- < 0.8 v. parameters symbol min. typ. max. units test conditions overtemp operate point (junction) t jop - 172 - c note 1 overtemp release point (junction) t jrp - 136 - c note 1 vcc bias voltage range v ccb 3.5 5 30 v vcc drivers voltage range v ccd 4.5 5 30 v supply current v ccb1 (bias) i ccb1 - 11.9 16.0 ma v ccb and v ccd = 5 v supply current v ccd1 (drivers) i ccd1 - 2.4 3.3 ma v ccb and v ccd = 5 v supply current v ccb2 i ccb2 - 2.5 3.4 ma v ccb and v ccd = 5 v, en- > 2 v supply current v ccd2 i ccd2 - 0.0 0.1 ma v ccb and v ccd = 5 v, en- > 2 v supply current v ccb3 i ccb3 - 12.1 18.5 ma v ccb and v ccd = 30 v supply current v ccd3 i ccd3 - 2.4 3.3 ma v ccb and v ccd = 30 v supply current v ccb4 i ccb4 - 2.6 3.5 ma v ccb and v ccd = 30 v, en- > 2 v supply current v ccd4 i ccd4 - 0.0 0.1 ma v ccb and v ccd = 30 v, en- > 2 v enable input threshold v the 0.8 1.5 2 v enable low level input current i ile -10 0 10 ? a v in = 0 v, v ccb = 5 v enable high level input current i ihe C 108 150 ? a v in = 5 v, v ccb = 5 v high impedance output leakage i oz -4.0 0.0 4.0 ? a v ccd = 30 v, en- > 2 v, output at 15 v input positive-going threshold v t+ 1.05 1.25 1.45 v v ccb = 5 v input negative-going threshold v t- 0.75 0.95 1.15 v v ccb = 5 v input hysteresis v h C 0.3 C v v ccb = 5 v low level input current i il -4.0 -0.1 - ? a v in = 0 v, v ccb = 5 v high level input current i ih - 0 4.0 ? a v in = 5 v, v ccb = 5 v low level output1 v ol1 - 375 500 mv i ol = 20 ma, v ccd = 5 v low level output2 v ol2 - 370 500 mv i ol = 20 ma, v ccd =30 v high level output1 v oh1 2.4 2.8 - v i oh = -20 ma, v ccd = 5 v high level output2 v oh2 27.7 28.1 - v i oh = -20 ma, v ccd =30 v note: 1. this is not a test parameter, but for information only. table 3. ac switching characteristics values given at v ccb = 5 v, v ccd = 24 v, t a = 25 c, c l = 1000 pf on all outputs, and en- < 0.8 v. parameters symbol min. typ. max. units test conditions propagation delay, rising input 50% point to zero crossing of diff erential outputs t plh - 450 630 ns see above. propagation delay, falling input 50% point to zero crossing of diff erential outputs t phl - 450 630 ns see above. output rise time t r - 700 980 ns see above. output fall time t f - 700 980 ns see above.
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2012 avago technologies. all rights reserved. av02-3021en - january 12, 2012 package drawings (dimensions in inches) notes: 1. lead coplanarity should be o to 0.004" max. 2. package surface fi nishing: vd1 24~27 (dual). package surface fi nishing: vd1 13~15 (16l soic(nb) matrix). 3. all dimension excluding mold fl ashes. 4. the lead width, b to be determined at 0.0075" from the lead tip. symbol 16 soic min max a 0.054 0.068 a1 0.004 0.0098 b 0.014 0.019 d 0.386 0.393 e 0.150 0.157 h 0.229 0.244 e 0.050 bsc c 0.0075 0.0098 l 0.016 0.034 x 0.020 ref 1 0 8 2 7 bsc d x e b e pin no. 1 id mark c l c l a a1 0.010 seating plane l detail a ? 2 gauge plane ? 1 0.004 detail a c h 0.015 x 45
|
